The present invention is generally directed to integrated circuits and, in particular, to a self-clocking, self-clearing latch that can be used with a short circuit detection circuit if a clock signal is not available.
In recent years, there have been great advancements in the speed, power, and complexity of integrated circuits, such as application specific integrated circuit (ASIC) chips, random access memory (RAM) chips, microprocessor (uP) chips, and the like. These advancements have made possible the development of system-on-a-chip (SOC) devices. A SOC device integrates into a single chip all (or nearly all) of the components of a complex electronic system, such as a wireless receiver (i.e., cell phone, a television receiver, and the like). SOC devices greatly reduce the size, cost, and power consumption of the overall system.
Many SOC devices contain peripheral device interfaces that communicate with external devices. For example, a SOC device may contain a Peripheral Component Interconnect (PCI) bus interface or a Universal Serial Bus (USB) interface communicating with one or more external devices. As part of a fault tolerant design, it is preferable to include short-circuit protection at an interface in order to protect the SOC device. If a short-circuit persists for more than a very brief period of time, the large current draw in the output line driver of the PCI bus interface or the USB interface may destroy the SOC device.
However, conventional short-circuit protection devices typically disable an interface or even an entire system if a short-circuit is detected. User intervention is then required to reset the device after the short-circuit has been removed.
Therefore, there is a need in the art for integrated circuits having improved short circuit protection. In particular, there is a need for a short-circuit protection apparatus for use in an electronic system that does not require user intervention to reset or re-enable the electronic system after a short-circuit has occurred.
The present invention provides a unique and novel circuit that can be used in an area of an integrated circuit, such as an SOC device, where a clock is not available. The present invention comprises an input stage that detects a rising signal edge (i.e., low to high transition), latches in the high signal, delays for a delay period determined by delay cells or an RC time constant, or both, and then clears the high signal from the latch. The present invention may also be modified to detect a high to low transition.
To address the above-discussed deficiencies of the prior art, it is a primary object of the present invention to provide a latch for detecting a state transition of an input signal and generating a self-clearing reset signal on an output. According to an advantageous embodiment of the present invention, the latch comprises: 1) a transfer gate capable of passing the input signal to a first node in the latch when the input transfer gate is enabled; 2) a transition detector capable of detecting a transition of the first node from a first state to a second state, wherein the transition detector, in response to the transition, disables the transfer gate and enables the reset signal; and 3) a feedback loop circuit capable of detecting enabling of the reset signal, wherein the feedback loop circuit, in response to the enabling, changes the first node from the second state back to the first state, and wherein the transition detector, in response to the changing of the first node back to the first state, disables the reset signal.
According to one embodiment of the present invention, the transition detector, in response to the changing of the first node back to the first state, enables the transfer gate.
According to another embodiment of the present invention, the transfer gate comprises an N-channel transistor in parallel with a P-channel transistor.
According to still another embodiment of the present invention, the transition detector generates a first control signal applied to a gate of the N-channel transistor of the transfer gate.
According to yet another embodiment of the present invention, the transition detector generates a second control signal applied to a gate of the P-channel transistor of the transfer gate.
According to a further embodiment of the present invention, the transition detector comprises a chain of inverters wherein an input of a first inverter of the chain of inverters is coupled to the first node and an output of a last inverter in the chain of inverters generates the reset signal.
According to a still further embodiment of the present invention, the feedback loop circuit comprises a drive transistor capable of changing the first node from the second state back to the first state.
According to a yet further embodiment of the present invention, the drive transistor discharges a capacitor coupled to the first node.
In one embodiment of the present invention, the feedback loop circuit further comprises a delay buffer having an input coupled to the reset signal and an output coupled to the drive transistor.
The foregoing has outlined rather broadly the features and technical advantages of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features and advantages of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they may readily use the conception and the specific embodiment disclosed as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.
Before undertaking the DETAILED DESCRIPTION OF THE INVENTION below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms xe2x80x9cincludexe2x80x9d and xe2x80x9ccomprise,xe2x80x9d as well as derivatives thereof, mean inclusion without limitation; the term xe2x80x9cor,xe2x80x9d is inclusive, meaning and/or; the phrases xe2x80x9cassociated withxe2x80x9d and xe2x80x9cassociated therewith,xe2x80x9d as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like; and the term xe2x80x9ccontrollerxe2x80x9d means any device, system or part thereof that controls at least one operation, such a device may be implemented in hardware, firmware or software, or some combination of at least two of the same. It should be noted that the functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior, as well as future uses of such defined words and phrases.